In a class D amplifier, the output stage is used as a switch for switching the output signal between a positive and a negative supply voltage in dependence of an input signal. The resulting output signal is therefore a pulse width modulated bipolar signal which may be demodulated by a demodulation filter and then be made audible by a loudspeaker.
The switching of the output stage typically switches one transistor of a pair of output transistors on while switching the other transistor off. When one of the output transistors is off, its current and hence its power dissipation are zero, resulting in a high efficiency, and relatively low power and cooling requirements.
Class D amplifiers are typically provided with an integrating analog feedback loop to reduce any distortion introduced by the output stage. To this end, the output signal is typically fed back to a pulse shaping circuit so as to adjust the pulse shaping in dependence of the output signal.
However, the gain of the feedback loop influences the modulation depth of the output signal. When the supply voltage decreases, for example, the feedback loop will adjust the pulse width (and hence the modulation depth) to compensate for the amplitude loss. This may cause the output signal of the amplifier to have a greater modulation depth than the input signal. Ultimately, the increased modulation depth may cause the output signal to clip to the supply voltage and stop changing sign. The integrator(s) involved in the feedback loop will then drift away from their normal operating range and also clip to a supply voltage. A class D amplifier is typically slow to recover from this condition, and the demodulated output signal may initially be distorted when the duty cycle returns to normal operating values.
U.S. Pat. No. 6,577,186 (Berkhout/Philips) discloses a class D amplifier comprising a pulse width modulation stage and a switching stage. An oscillator provides a clock signal to a second integrator of the pulse width modulation stage, while a feedback loop feeds the output signal back to a first integrator of the pulse width modulation stage. To prevent or limit clipping, a pulse width modulation limiter is provided to effectively limit the modulation depth. This Prior Art pulse width modulation limiter is arranged between the pulse width modulation stage and the switching stage, and receives both the comparator signal and the clock signal to produce a minimum width output pulse on an edge of the clock signal. These minimum width output pulses ensure that a carrier frequency is always present in the output signal, and allow any bootstrap capacitors present in the switching output unit to be recharged regularly, thus ensuring a proper functioning of the switching output unit.
Although the arrangement of U.S. Pat. No. 6,577,186 operates well, its use is limited to class D amplifiers having a clock generator. It has been found that a clock generator can be dispensed width if the input signal is a digital signal, for example a PDM (Pulse Density Modulation) signal or a PWM (Pulse Width Modulation) signal. In addition, this Prior Art solution effectively forces the output to change sign but still allows the integrators to run away, thus only offering a partial solution to the problem.